I've noticed a few common typos lately that cause a bit of disoragnization for the pages on this site. I thought I'd point them out in a quick post (in case anyone feels like reading it). The first has to do with the syntax for blog tags. You should list each tag inside square brackets "[", "]" and separate each tag by a comma and a space, not just a space. If you use a space, it will create a tag that has a space in it. For example, [gpgpu sphynx] will create a tag with the text "gpgpu sphynx"...

UPDATE: I included a list of things to take away from the paper after our meeting today. __ The paper is about compiling a program in memory in an “Instruction cache aware” way to minimize cache conflicts between procedures. The main issue is the conflicts between procedures on different threads (inter-thread account for an average of 21.21% of misses, usually due to the processor switching between threads often every cycle) than on the same thread (intra-thread accounts for an average of 20.47% of all misses, usually due to procedure calls). Inter-thread conflicts tend to not repeat with predictable patterns, making...

I read about caches, instruction caches, their applications, and ongoing research about them. First of all, a cache is where on can visibly store data. This makes retrieving data significantly faster. If the correct data is sucessfully retrieved, it is a cache hit. If not, it is a cache miss. If more requests for data can be made from the cache, the performance will be much faster. Caches are usually small for efficiency, especially cost-efficiency. This is alright because referencs generally have locality of reference, or make multiple requests for the same data, as opposed to always requesting different data....

The CPU cache stores copies of data from frequently used memory locations. This allows the run time of the CPU to be much shorter since drawing/reading memory from the main memory locations requires more time. The cache memory is always a first step for the CPU when writing or reading data. If the data being written/read is already present in the cache, it does not need to access main memory which saves time. Three main types of caches: Instruction Cache: easy access to instruction data Data Cache: easy access to data Translation Lookaside Buffer (TLB): used to speed up virtual-physical...

CASE STUDY: PENTIUM 4 CACHE ORGANIZATION All Pentium processors have 2 on-chip L1 caches – one for data caches and the other for instruction caches. The Pentium 4 has an L2 cache which feeds off both the L1 caches. These are the components of the processor core for the Pentium 4: Fetch/decode unit: Fetches instructions from the L2 cache, breaks them into simpler micro instructions and then feeds it to the L1 cache. Out of order execution logic: This logic executed the instructions retrieved and in the L1 cache. However, it executes them on the basis of data dependencies and...

I've created a Google Group for private communication. If you aren't in it and you think you should be, send me an email. I took a look at GPGPU-Sim to get an idea of how it is working. I was pleased to find that the code is pretty nicely organized and well written. I generated the Doxygen, however it seemed a little odd. Although there was some information on GPGPU-Sim, there was also a good deal about an XMLParser library, which seems completely unrelated. Here's what I was able to gather by poking around in the source. The gpgpu repo...

I wanted a place to compile what I found about how to get GPGPU sim up and running on Tera and make a list of the things that needs to be sort out. First off, here are the list of dependencies that we need to get installed on linux to build the code(from README document). The items in bold are the dpendencies that need to be installed on Tera. Ones not in bold have already been installed. GPGPU-Sim dependencies: gcc g++ make makedepend xutils bison flex zlib CUDA Toolkit GPGPU-Sim documentation dependencies: doxygen graphvi As shown above, to run GPGPU-sim,...

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