2014-2-25-Minutes
Here are the minutes from 2/25/14.
In Attendance: Prof Spjut, Donghyeon, Fabiha, and Akhil Start time: 12:05 pm End time: 1:01 pm
Updates:
Akhil finished running the instruction counter for all of the benchmarks. This blog post has been updated with the numbers.
I finished writing a parser to extract information and calculate the stalls due to the instruction cache. I couldn't work on the instruction duplication because we have not yet edited and looked at the banks.
Donghyeon edited the instruction cache output to display the stats for each core's performance and made a more thorough list of each benchmark and its characteristics. These are in these two blog posts respectively: Instruction Cache Output and Sphynx Benchmarks.
Things to do this week:
Make a table of GPU architectures & specs (Akhil)
Work on the parser (Fabiha)
See if =decreasing cache size makes a difference (same block size, reduce blocks to 1 set for 4-way set associativity (or from 1024 bytes to 512 bytes)) in the misses (Donghyeon)
Independent assignment for everyone:
a) Come up with designs for shared cache [note: instruction memory tends to have sequential pattern & temporal repetition (loop)]
b) Skim a micro paper from last year and get a feel of what it should look like (Micro 2013 paper microarch.org)
Other notes:
The default for instruction caches: instruction copied to each core and must merge 2 cores (aka put execution units together) to get it to share
We are submitting to the IEEE microarchitecture conference: middle to end of May, we need it done at the beginning of May to submit to peer review